The invention relates generally to the art of microelectronic integrated circuit layout, and more specifically to methods for substrate component placement to avoid overcrowding of a substrate surface.
Microelectronic integrated circuits consist of a large number of electronic components, including individual logic devices or groups of logic devices that are applied to the surface of a substrate, typically a silicon wafer. The components are typically grouped to provide an application-specific integrated circuit. For each application-specific integrated circuit, placement of the components in optimum positions provides efficient layout of the components on the substrate in order to reduce manufacturing costs, processor delays, size and the like. Because the application-specific integrated circuits typically contain hundreds of thousands, if not millions of components, the task of optimizing the placement of components on a substrate surface is not practical without the aid of computers.
Computer aided designs are effective to provide component location on the substrate surface for minimizing interconnection distances, wire sizes, processing times and the like. The smallest component placed on a substrate surface is defined as a xe2x80x9ccell.xe2x80x9d A cell may be a single logic component of a larger logic tree or may be one or more logic trees. Assuming the number of cells N to be in the hundreds of thousands or millions, the number of different ways that the cells can be arranged on the substrate surface is equal to about N factorial. Selecting the optimum placement of the cells is therefore an extremely time consuming task.
Furthermore, despite the use of computer aided design techniques, algorithms used for selecting cell locations on the substrate surface may lead to cell congestion or overpopulation of cells in an area of the substrate surface. Overpopulation or overcrowding of an area of the substrate surface is undesirable from the standpoint of enabling efficient wiring routes, reducing overlapping circuits and the like. Accordingly, there continues to be a need for methods useful to further improve the cell placement on a substrate surface in order to lower substrate costs and increase processor speeds.
With regard to the above and other objects and advantages, the invention provides a method for selectively placing cells of an application-specific integrated circuit on a substrate surface. The method includes the steps of:
a) defining a grid covering a substrate surface,
b) assigning cells to the grid to provide old x and y coordinates of the cells relative to the grid,
c) grouping the cells by function to provide functional regions within the grid,
d) determining a density map of the surface of the substrate in all the functional regions within the grid,
e) determining free space of the grid on the surface of the substrate relative to the density map, and
f) assigning new cells to the free space of the grid on the substrate surface to provide an application specific integrated circuit.
In another aspect the invention provides a method for reducing noise and congestion for substrate components on a substrate surface during a substrate component placement procedure for an application-specific integrated circuit. The method includes the steps of:
a) providing a grid covering the surface of the substrate defining old x and y coordinates of a cell and an old cell origin point for each cell to be placed on the substrate surface,
b) shifting all old cell origin points to a center of its corresponding cell,
c) flipping or rotating the cells to provide new cell origin points,
d) determining an approximate density map of the substrate surface based on the new cell origin points,
e) selecting new x and y cell coordinates of the cells at the new cell origin points,
f) optimizing the new x and y cell coordinates, and
g) determining an actual density map of the substrate surface based on the cell placement after optimization thereof.
In yet another aspect the invention provides a computing device for optimizing design of a semiconductor substrate layout. The computing device includes a memory for storing process steps including the steps of:
a) defining a grid covering a substrate surface,
b) assigning cells to the grid to provide old x and y coordinates of the cells relative to the grid,
c) grouping the cells by function to provide functional regions within the grid,
d) determining a density map of the surface of the substrate in all the functional regions within the grid,
e) determining free space of the grid on the surface of the substrate relative to the density map, and
f) assigning new cells to the free space of the grid on the substrate surface to provide an application specific integrated circuit
In another aspect, the invention provides a physical media readable by a computerized system. The physical media includes a computer program for layout design and configuration of a semiconductor substrate, the program including the steps of:
a) defining a grid covering a substrate surface,
b) assigning cells to the grid to provide old x and y coordinates of the cells relative to the grid,
c) grouping the cells by function to provide functional regions within the grid,
d) determining a density map of the surface of the substrate in all the functional regions within the grid,
e) determining free space of the grid on the surface of the substrate relative to the density map, and
f) assigning new cells to the free space of the grid on the substrate surface to provide an application specific integrated circuit.
An important advantage of the invention is that it provides a semiconductor substrate layout having minimal cell congestion or overlapping thereby improving the utilization of the substrate surface more effectively.